The present invention relates to a vertical filter circuit which is employed in a television receiver, a video tape recorder or a like apparatus having the picture-in-picture function of displaying a main picture together with one or more inserted sub-pictures.
In order to produce a sub-picture obtained by the reduction of an original picture at a predetermined reduction ratio, a television receiver having the picture-in-picture function comprises, as shown in FIG. 1, a matrix circuit 11, an analog-to-digital converter (an A/D converter) 12, a serial-to-parallel converter (an S/P converter) 13 and a vertical filter circuit 20. Here, a video signal of the original picture is inputted into the matrix circuit 11 as a brightness signal Y and two color difference signals R-Y, B-Y. The matrix circuit 11 comprises one clamping circuit and three multiplexers, and samples a brightness signal Y received from a Y/C separation circuit (not shown) and two color difference signals R-Y, B-Y received from a color demodulation circuit (not shown) at a predetermined clock timing to fetch the video signal as an internal signal. That is, in the matrix circuit 11, the brightness signal Y is clamped to a predetermined clamp level by the clamping circuit and then sampled at a clock timing of 9 MHz by one of the multiplexers while two color difference signals R-Y, B-Y are clamped to a predetermined clamp level by the clamping circuit and then sampled at a clock timing of 2.25 MHz by the respective remaining multiplexers. Consequently, the video signal is fetched as an internal signal, each unit of which consists of signals for eight picture elements including brightness signals Y for four picture elements, one color difference signal R-Y for one picture element and another color difference signal B-Y for one picture element. For example, a serial video signal, one unit of which consists of (Y)-(R-Y)-(Y)-(blank)-(Y)-(B-Y)-(Y)-(blank) for eight picture elements, is outputted from the matrix circuit 11 to the A/D converter 12. The A/D converter 12 samples the serial video signal with a sampling clock of 18 MHz to convert the serial video signal into a digital serial video signal. The S/P converter 13 converts the digital serial video signal which is received from the A/D converter 12 into a digital parallel video signal. That is, when the digital serial video signal is inputted from the A/D converter 12 to the S/P converter 13, for example, in the order of (Y)-(R-Y)-(Y)-(blank)-(Y)-(B-Y)-(Y) (blank), the digital serial video signal is converted into one digital parallel video signal of (Y, R-Y, Y) and another digital parallel video signal of (Y, B-Y, Y).
The vertical filter circuit 20 comprises a shifter 10 21 connected to the S/P converter 13, first to third delay circuits 30.sub.1 -30.sub.3 connected to the S/P converter 13, a calculation circuit 22 connected to the shifter 21 and the first to third delay circuits 30.sub.1 -30.sub.3, and a buffer memory 23 connected to the calculation circuit 22. The first delay circuit 30.sub.1 comprises a first write selector 31.sub.1, a first line memory 32.sub.1, a first read selector 33.sub.1 and a first shifter 34.sub.1 which are connected in series. The second delay circuit 30.sub.2 comprises a second write selector 31.sub.2, a second line memory 32.sub.2, a second read selector 33.sub.2 and a second shifter 34.sub.2 which are connected in series. The third delay circuit 30.sub.3 comprises a third write selector 31.sub.3, a third line memory 32.sub.3, a third read selector 33.sub.3 and a third shifter 34.sub.3 which are connected in series.
The shifter 21 comprises a shift register and shifts the digital parallel video signal received from the S/P converter 13 the number of bit positions corresponding to the reduction ratio of the sub-picture in order to allow the averaging process which is required when the sub-picture is to be produced. Each of the write selectors 31.sub.1 -31.sub.3 comprises the number of clocked inverters equal to the number of bits of the digital parallel video signal, and only one of the write selectors 31.sub.1 -31.sub.3 is selected in accordance with a write select signal (not shown) inputted from the outside. Each of the line memories 32.sub.1 -32.sub.3 is used to store therein the digital parallel video signal for one scanning line received from the S/P converter 13 by way of the corresponding write selector of the write selectors 31.sub.1 -31.sub.3. Each of the read selectors 33.sub.1 -33.sub.3 comprises the number of clocked inverters equal to the number of bits of the parallel signal, and only one of the read selectors 33.sub.1 -33.sub.3 is selected in accordance with a read select signal (not shown) inputted from the outside. Each of the shifters 34.sub.1 -34.sub.3 comprises a shift register and shifts the digital parallel video signal received from the corresponding line memory of the line memories 32.sub.1 -32.sub.3 by way of the corresponding read selector of the read selectors 33.sub.1 -33.sub.3 the number of bit positions corresponding to the reduction ratio of the sub-picture in order to allow the averaging process. The calculation circuit 22 is used to effect the calculation necessary for the production of image data for the sub-picture using the digital parallel video signals which are received from each of the shifters 21 and 34.sub.1 -34.sub.3. The buffer memory 23 is used to temporarily store the image data for the sub-picture which is outputted from the calculation circuit 22.
Next will be described the operation using the vertical filter circuit 20 for producing a sub-picture reduced to one ninth in size.
In order to produce image data for a sub-picture reduced to one ninth in size in relation to the vertical direction of the screen, one scanning line should be extracted from every three adjacent scanning lines. However, the simple extraction of one scanning line from every three adjacent scanning lines will result in the deterioration of the picture quality of the sub-picture. Accordingly, a common practice is to effect an averaging process for every three successive scanning lines to extract a single scanning line. That is, where a first digital parallel video signal of the first one of three successive scanning lines on the screen is represented by "L.sub.n-1, " , a second digital parallel video signal of the second scanning line by "L.sub.n " and a third digital parallel video signal of the third scanning line by "L.sub.n-1," a single scanning line is extracted from the three scanning lines by calculating the digital parallel video signal K.sub.n in accordance with the following equation: EQU K.sub.n =(L.sub.n-1 +2L.sub.n +L.sub.n+1)/4 (1)
Accordingly, when the first digital parallel video signal L.sub.n-1 from among three successive scanning lines 10 is inputted from the S/P converter 13 to the vertical filter circuit 20, only the first write selector 31.sub.1 is selected in accordance with the write select signal described above. Consequently, the first digital parallel video signal L.sub.n-1 is stored into the first line memory 32.sub.1. When the second digital parallel video signal L.sub.n is inputted from the S/P converter 13 to the vertical filter circuit 20, only the second write selector 31.sub.2 is selected in accordance with the write select signal so that the second digital parallel video signal L.sub.n is stored into the second line memory 32.sub.2. When the third digital parallel video signal L.sub.n+1 is inputted from the S/P converter 13 to the vertical filter circuit 20, none of the write selectors 31.sub.1 -31.sub.3 is selected so that the third digital parallel video signal L.sub.n+1 is inputted to the calculation circuit 22 by way of the shifter 21.
Thereafter, the first read selector 33.sub.1 and the second read selector 33.sub.2 are selected in accordance with the read select signal described above so that the first digital parallel video signal L.sub.n-1 stored in the first line memory 32.sub.1 and the second digital parallel video signal L.sub.n stored in the second line memory 32.sub.2 are inputted to the calculation circuit 22 by way of the first shifter 34.sub.1 and the second shifter 34.sub.2, respectively. In this instance, in order to effect the averaging process represented by equation (1) above, the first digital parallel video signal L.sub.n-1 is inputted to the calculation circuit 22 without being shifted by the first shifter 34.sub.1, while the second digital parallel video signal L.sub.n is shifted right one bit position by the second shifter 34.sub.2 to double it and then inputted to the calculation circuit 22. The third digital parallel video signal L.sub.n+1 is inputted to the calculation circuit 22 without being shifted by the shifter 21. In the calculation circuit 22, the digital parallel video signals L.sub.n-1, L.sub.n and L.sub.n+1, which are inputted from the first shifter 34.sub.1, the second shifter 34.sub.2, and the shifter 21, respectively, are added for each picture element and then multiplied by 1/4 to make the digital parallel video signal K.sub.n which represents the image data for the sub-picture. The digital parallel video signal K.sub.n is outputted to the outside by way of the buffer memory 23.
It is to be noted that, in order to produce the image data for the sub-picture reduced to one ninth in size in relation to the vertical direction of the screen, only one of every three adjacent scanning lines should be extracted. Accordingly, the first and second delay circuits 30.sub.1, 30.sub.2 are used. However, in order to produce image data for a sub-picture reduced in size to one sixteenth in relation to the vertical direction of the screen, one of every four successive scanning lines should be extracted. In this case, all of the first to third delay circuits 30.sub.1 -30.sub.3 are used. On the other hand, in order to produce image data for a sub-picture reduced to one fourth in size in relation to the vertical direction of the screen, one of every successive two scanning lines should be extracted. In this case, only the first delay circuit 30.sub.1 is used.
As described above, the vertical filter circuit 20 comprising the three delay circuits 30.sub.1 -30.sub.3 can produce the image data for sub-pictures reduced to one fourth, one ninth, and one sixteenth in size. However, since the number of delay circuits depends on the size of the sub-picture, when producing LSI chips, there is a problem that a large area is required for line memories and signal lines, and consequently a large chip size is required. In order to produce the image data for a sub-picture reduced to one ninth in size, the averaging process is not performed until after all of the digital parallel video signals L.sub.n-1, L.sub.n and L.sub.n+1 of the three successive scanning lines are inputted to the vertical filter circuit 20. Accordingly, there is another problem that much time is required to produce the image data for the sub-picture.